How this works
Many simple I2C peripherals derive SCL frequency as roughly Fclk / (2 × divider) for a symmetric clock, though the exact formula (and any added rise-time compensation terms) varies significantly by vendor — some use separate high/low period registers instead of a single divider. Treat this as a starting estimate and confirm against your specific I2C controller's reference manual, especially for fast-mode (400kHz) or fast-mode-plus targets where rise-time compensation matters more.